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    “111”引智平臺“高等并行計算機系統結構”系列講座—Does Hardware Design have to be Hard?

    發布時間: 2014-09-18     作者:欒鐘治    點擊次數:

    報告題目:Does Hardware Design have to be Hard?
    報告人:James Hoe, Professor, IEEE Fellow, Carnegie Mellon University, USA
    報告時間:9月22-26日9:00-12:00
    報告地點:新主樓F座327

    內容簡介:
    Does Hardware Design have to be Hard?

    VLSI technology trend dictates that continued performance scaling in computation must be accompanied by expending less energy per operation. Mapping computations directly onto hardware—avoiding the execution overhead of software—is the most direct way to achieve the needed energy/power reduction for the most performance demanding applications. The increasingly capable FPGA co-processing options emerging in the last few years have reduced the barrier-to-entry from a platform perspective. Still, a major obstacle to a more widespread use of hardware acceleration remains in the high degree of difficulty in mapping applications to hardware.

    This short course addresses the question, does hardware design have to be hard, especially in the context of mapping computation to hardware for acceleration. The scope of the course is based on the research experience and perspectives of the instructor. This course does not assume a background in digital logic and hardware design and will provide an overview of the essential background concepts. The major topics to be discussed in this short course are

    ? Operation-Centric Hardware Design and Synthesis (Bluespec)

    ? C-to-Hardware Design and Synthesis

    ? Domain-Specialized High-level Synthesis (Spiral)

    ? “Smart” IP-Based Design (Pandora)

    ? Infrastructure and Virtualization (CoRAM)

    ? Performance, Power and Energy of Hardware Acceleration

    There will be approximately 2 hours of slide-based presentation and 1 hour of open discussion per day for this 5-day short course.

    課程相關資料:
    http://users.ece.cmu.edu/~jhoe/doku/doku.php?id=bhsc14

    教授簡介:
    James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University. He received his Ph.D. in EECS from Massachusetts Institute of Technology in 2000 (S.M., 1994). He received his B.S. in EECS from UC Berkeley in 1992. He is interested in many aspects of computer architecture and digital hardware design, including the specific areas of FPGA architecture for computing; digital signal processing hardware; and high-level hardware design and synthesis. He co-directs the Computer Architecture Lab at Carnegie Mellon (CALCM) and is affiliated with the Center for Silicon System Implementation (CSSI). He is a Fellow of IEEE. For more information, please visit http://www.ece.cmu.edu/~jhoe.

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